Random access memory (RAM) is commonly provided in computer systems. Common architectures provide RAM that can be embodied as a stand alone device or can be integrated or embedded within devices such as microprocessors, microcontrollers, application specific integrated circuits (ASICs), system-on-chip (SoC), and other like devices, as will be appreciated. Volatile RAM loses its stored information whenever power is removed. Non-volatile RAM can maintain its memory contents even when power is removed from the memory. Although nonvolatile RAM has advantages, conventional non-volatile RAM has slower read and write times when compared to, for example, volatile RAM.
Advanced memory technology has evolved to provide increasing access speed even for non-volatile memory types. For example, Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that has read and write response times comparable to that of volatile memory. In contrast to conventional RAM technologies, which store data as electric charges or current flows, MRAM uses magnetic elements. As illustrated in FIG. 1A and FIG. 1B, a magnetic tunnel junction (MTJ) storage element 100 can be formed from two magnetic layers 110 and 130, each of which can hold a magnetic field, separated by an insulating layer 120, which can be, for example a tunnel barrier layer, or the like. One of the two layers such as fixed layer 110, is set to a particular polarity. The polarity 132 of the other layer, such as free layer 130, is free to change to match that of an external field that can be applied. A change in the polarity 132 of the free layer 130 will change the resistance of the MTJ storage element 100. For example, as shown in FIG. 1A, when the polarities are aligned, a low resistance state exists. When the polarities are not aligned, as shown in FIG. 1B, a high resistance state exists. The illustration of MTJ 100 has been simplified and it will be appreciate that each layer illustrated may include one or more layers of materials, as is known in the art.
Referring to FIG. 2A, a memory cell 200 of a conventional MRAM is illustrated for a read operation. The cell 200 includes a transistor 210, bit line 220, digit line 230 and word line 240. The cell 200 can be read by measuring the electrical resistance of the MTJ 100. For example, a particular MTJ 100 can be selected by activating an associated transistor 210, which can switch current from a bit line 220 through the MTJ 100. Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers (e.g., 110, 130), as discussed above. The resistance inside any particular MTJ 100 can be determined from the current, resulting from the polarity of the free layer. Conventionally, if the fixed layer 110 and free layer 130 have the same polarity, the resistance is low and a “0” is read. If the fixed layer 110 and free layer 130 have opposite polarity, the resistance is higher and a “1” is read.
Referring to FIG. 2B, the memory cell 200 of a conventional MRAM is illustrated for a write operation. The write operation of the MRAM is a magnetic operation. Accordingly, transistor 210 is off during the write operation. Current is propagated through the bit line 220 and digit line 230 to establish magnetic fields 250 and 260 that can affect the polarity of the free layer of the MTJ 100 and consequently the logic state of the cell 200. Accordingly, data can be written to and stored in the MTJ 100. MRAM has several desirable characteristics that make it a candidate for a universal memory. The characteristics can include high speed, high density or small bitcell size, low power consumption, and no degradation over time. However, MRAM has scalability issues. Specifically, as the bit cells become smaller, the magnetic fields used for switching the memory state increase. Accordingly, current density and power consumption increase to provide the higher magnetic fields, thus limiting the scalability of the MRAM.
Unlike conventional MRAM, STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film which functions as a spin filter. STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer. The read operation is similar to conventional MRAM in that a current is used to detect the resistance or the logic state of the MTJ storage element, as discussed in the foregoing. As illustrated in FIG. 3A, a STT-MRAM bit cell 300 includes MTJ 305, transistor 310, bit line 320 and word line 330. The transistor 310 is switched on for both read and write operations to allow current to flow through the MTJ 305, so that the logic state can be read or written.
Referring to FIG. 3B, a more detailed diagram of a STT-MRAM cell 301 is illustrated, for further discussion of the read/write operations. In addition to the previously discussed elements such as MTJ 305, transistor 310, bit line 320 and word line 330, a source line 340, sense amplifier 350, read/write circuitry 360 and bit line reference 370 are illustrated. As discussed above, the write operation in an STT-MRAM is electrical. Read/write circuitry 360 generates a write voltage between the bit line 320 and the source line 340. Depending on the polarity of the voltage between bit line 320 and source line 340, the polarity of the free layer of the MTJ 305 can be changed and correspondingly the logic state can be written to the cell 301. Likewise, during a read operation, a read current is generated, which flows between the bit line 320 and source line 340 through MTJ 305. When the current is permitted to flow via transistor 310, the resistance (logic state) of the MTJ 305 can be determined based on the voltage differential between the bit line 320 and source line 340, which is compared to a reference 370 and then amplified by sense amplifier 350. It will be appreciated that the operation and construction of the memory cell 301 is known in the art. Additional details are provided, for example, in M. Hosomi, et al., A Novel Nonvolatile Memory with Spin Transfer Torque Magnetoresistive Magnetization Switching: Spin-RAM, proceedings of IEDM conference (2005), which is incorporated herein by reference in its entirety.
The electrical write operation of STT-MRAM eliminates the scaling problem due to the magnetic write operation in MRAM. Further, the circuit design is less complicated for STT-MRAM. In a conventional arrangement of the STT-MRAM array, such as illustrated in FIG. 4A, the source line (SL) is orthogonal to word line (WL) and is parallel with the bit line (BL). This arrangement increases the area used for the bit cell array and results in large bit cell size. The conventional arrangement promotes a stable write operation. For example, during the write operation, for writing a state of “1” the following conditions are satisfied WL=H, BL=L and SL=H for the selected bit cell 410 and a proper write operation can be performed. As used herein H represents a high voltage or logic level and L represents a low voltage or logic level. For the unselected bit cells 420, the WL=H, BL=L and SL=L and thus there is no invalid write operation on the unselected bit cells. However, while aiding in preventing invalid write operations, the conventional arrangement is inefficient in the area used per bit cell since the line cannot be shared which results in additional metal 1 which is illustrated as “SL(M1)” for a source line as shown in FIG. 4B. As further illustrated in the circuit layout of FIG. 4B, each bit line (BL) can be located on another metal layer “Mx” running substantially in parallel with the source lines.